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data brief for further information contact your local stmicroelectronics sales office. october 2011 doc id 022239 rev 1 1/27 1 stm7007 single-chip hardware accelerated encryption engine for computer and peripherals applications features world class encryption engine ? hardcache? crypto module ? fips 140-2 security level 3 ? nist certificate #1599 symmetric algorithms (nist fips approved) ? aes rijndael block cipher: key length 128/192/256 bits, ecb/cbc/cbc-fve modes, nist certificate #1068 ? triple des: key length 112/168 bits, ecb/cbc modes, nist certificate #798 ? sha-256, sha-384 and sha-512 with associated hmac: nist shs certificate #1015, nist hmac certificate #606 asymmetric algorithms ? ecdsa, 256- and 384-bit elliptic curves ? rsa pkcs#1 v2.1 padding scheme ? 2048 bit operands algorithm control policy ? easy algorithm configuration ? export control pci express ? x1 interface advanced 65 nm process technology windows xp, windows 2000, windows vista, windows 7 (a) ecopack ? rohs compliant system benefits off-loads intensive cryptographic calculations (asymmetric and symmetric) from the system cpu out performs sw based solutions and 3 ghz processors full duplex dma operation best in class performance / power ratio secure key management protected inside a tamper resistant cryptographic boundary resists attacks that use software and/or instrumentation monitors enables secure remo te administration shielded locations and protected operations applications desktop pc clients laptop and mobile pc server and workstation entire volume encryption data loss protection cryptographic service provider secure messaging description the stm7007 is a pci express encryption engine built on the stmicroelectronics? hardcache? cryptograph ic channel controller (a high performance core computing block, with fips 140-2 security le vel 3 certification). the stm7007 provides hardware acceleration for commonly used algorithms, including aes, 3des, sha, hmac, rsa, and ecc. a. windows is a trademark of microsoft corporation. www.st.com
contents stm7007 2/27 doc id 022239 rev 1 contents 1 device pinout and package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 device pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 device package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2.1 dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2.2 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.3 markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2.4 recommended land pad layout and solder reflow profile . . . . . . . . . . . 11 1.2.5 rework guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 environment maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 dc electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5.1 pci, miscellaneous 3.3v interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5.2 phy 1.2v and 2.5v interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6 ac electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7 differential interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . 17 2.7.1 pcie test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 pcb layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 pcb routing of rx/tx differential signals . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.1 example: pcb impedance calculation . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 pcb power and ground decoupling guidelines . . . . . . . . . . . . . . . . . . . . 22 3.3 power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
stm7007 device pinout and package doc id 022239 rev 1 3/27 1 device pinout and package device pinout, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 device pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 signal types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 signal groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 stm7007 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 device package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 1. device pinout, top view refclkp refclkn vddpll1v2 vddt1v2 pern perp vddr1v2 rsvd petn petp vdd1v2 rsvd rsvd rsvd perst# rsvd refres gnd_pll vddpll2v5 vdd1v2 rsvd rsvd rsvd pgood clkreq# rsvd rsvd vdd2v5 rsvd rsvd rsvd vdd3v3 1 8 2 3 4 5 6 7 9 16 10 11 12 13 14 15 25 32 26 27 28 29 30 31 24 17 23 22 21 20 19 18 stm7007 32-pin lga 5x5 gnd
device pinout and package stm7007 4/27 doc id 022239 rev 1 1.1 device pins ta bl e 1 lists the abbreviations used for the signal type names in ta bl e 3 . note that abbreviations may be combined, as with apwr (analog power supply). ta bl e 2 lists device signals and how they are grouped, color coding each group. ta bl e 3 lists device pins, and uses the same color coding as ta b l e 2 to indicate pin grouping. table 1. signal types abbreviation description aanalog di digital input do digital output gnd ground i input lvdsi low voltage differential input lvdso low voltage differential output nc no connection o output pwr power supply table 2. signal groups signal group count (32-pin lga 5x5 package) vdd1v2, vdd2v5, vdd3v3, vdd1v2, vddpll1v2, vddpll2v5, vddr1v2, vddt1v2 power (vdd) 8 vss_pll, vss ground (vss) 2 (gnd pad slug on bottom of device) petp, petn, perp, pern, refclkp, refclkn, clkreq#, perst# pci express 8 refres, pgood misc 3 rsvd not connected 3 table 3. stm7007 pins pin number pin name signal type (1) external component description 1 refclkp lv d s i ? low voltage differential clock input 2 refclkn 3 vddpll1v2 apwr decoupling capacitor 1.2 volt analog power input for the internal pll block 4 vddt1v2 apwr decoupling capacitor 1.2 volt analog power input for pcie transmit channel
stm7007 device pinout and package doc id 022239 rev 1 5/27 5 pern lv d s i ? low voltage differential receive pair 6 perp 7 vddr1v2 apwr decoupling capacitor 1.2 volt analog power input for pcie receive channel 8 rsvd nc reserved pins, do not connect 9 petn lv d s o ? low voltage differential transmit pair 10 petp 11 vdd1v2 pwr decoupling capacitor 1.2 volt power supply input for core 12 rsvd nc ? reserved 13 rsvd nc ? reserved 14 rsvd nc ? reserved 15 perst# di ? asynchronous device reset input from system. when asserted, stm7007 resets all volatile content and executes a reboot after de-assertion of signal. 16 rsvd nc ? reserved 17 vdd3v3 pwr decoupling capacitor 3.3 volt power supply input for i/o logic 18 rsvd nc ? reserved 19 rsvd nc ? reserved 20 rsvd nc ? reserved 21 vdd2v5 pwr decoupling capacitor 2.5 volt power supply 22 rsvd nc ? reserved pins, do not connect 23 24 clkreq# do ? informs the host controller that the reference clock input is required by the stm7007. it is an open drain active low output; when 0, the reference clock is required, otherwise the reference clock can be off. 25 pgood di ? power on reset, used to reset the core. 26 rsvd nc ? reserved 27 rsvd nc ? reserved 28 rsvd nc ? reserved 29 vdd1v2 pwr decoupling capacitor 1.2 volt power supply input for core 30 vddpll2v5 pwr ? 31 gnd_pll gnd ? dc return pin for pll block table 3. stm7007 pins (continued) pin number pin name signal type (1) external component description
device pinout and package stm7007 6/27 doc id 022239 rev 1 32 refres ai resistor reference resistor input for pll block. this pin is tied to 1.2v pll using a 475_1% ohm resistor ? gnd gnd - dc return pad 1. for acronym definitions, see table 1: signal types on page 4 . table 3. stm7007 pins (continued) pin number pin name signal type (1) external component description
stm7007 device pinout and package doc id 022239 rev 1 7/27 1.2 device package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 this device uses a 32-lead, 5 x 5 x 0.82 mm land grid array (lga) package. note: 1 this package is not yet defined in jedec publications. 2 the exact shape of each corner is optional.
device pinout and package stm7007 8/27 doc id 022239 rev 1 1.2.1 dimensions table 4. package dimensions (mm) reference minimum typical maximum a 0.74 0.82 0.88 a1 0.00 0.035 a3 0.22 b 0.18 0.25 0.30 d 4.90 5.00 5.10 d1 3.50 d2 2.65 2.70 2.75 e 4.90 5.00 5.10 e1 3.50 e2 2.65 2.70 2.75 e0.50 l0.35 0.45 l1 0.075 ddd 0.100
stm7007 device pinout and package doc id 022239 rev 1 9/27 1.2.2 recommended footprint figure 2. pcb layout recommendation figure 3. stencil layout recommendation gnd via ( 8 ) pcb_met a l: 250 x 3 25 m (1 to 1 r a tio to p a ck a ge p a d) pcb_ s older m as k opening: 3 00 x 3 75 m gnd p a d pcb met a l: 3 600 x 3 600 m ep a d s oldering are a (5) pcb_ s older m as k opening: 700 m di a . s tencil thickne ss : 4 mil s l a nd a pert u re: 250 x 3 25 m (1 to 1 r a tio) ep a d s oldering a pert u re: 750 u di a . ( s light incre as e) thicker s tencil option s tencil thickne ss : 5 mil s l a nd a pert u re: 275 x 3 57 m (10 % incre as e) ep a d s oldering a pert u re: 8 00 m di a . for a thicker s tencil, s lightly incre as e the a pert u re s ize for ro bus t s older p as te rele as e (incre as e a re a r a tio: a re a of p a d / a re a of a pert u re w a ll).
device pinout and package stm7007 10/27 doc id 022239 rev 1 1.2.3 markings device base number: 7007 (four digits) device revision number: n . n n = full-layer revision number (one digit) n = metal revision number (one digit) figure 4. device markings (package face: top) in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. assembly date (y/ww) st logo 2nd level interconnect (e2) (an ecopack ? parameter) ecopack ? grade metal revision # ( n of n.n ) assembly sub lot diffusion plant device base number country of origin assembly plant back-end sequence orientation dot n 7007n full-layer revision # ( n of n.n ) pci gen1 or gen2 (1 or 2)
stm7007 device pinout and package doc id 022239 rev 1 11/27 1.2.4 recommended land pad lay out and solder reflow profile pay special attention to the traces connecting to the metal pads on the board. trace cracking can occur during normal handling of the board. this trace cracking usually occurs at the edge of the solder mask opening, around the metal pad. to avoid this mode of failure, make the trace under the solder mask edge wider than the rest of the trace, as shown in figure 5 . depending on t he reliability requirements of the connection, the wider part of the trace might need to be as wide as 50 to 75% of the metal pad width. figure 5. wider trace connection to avoid cracking
device pinout and package stm7007 12/27 doc id 022239 rev 1 solder flow profile reflow profile and peak temperature have a strong influence on void formation. follow the profile recommendation of the paste suppliers, be cause this is specific to the requirements of flux formation. the following two profiles can serve as reference for fine tuning the final profile that works for your application. figure 6. snpb solder flow profile figure 7. pb-free solder flow profile
stm7007 device pinout and package doc id 022239 rev 1 13/27 1.2.5 rework guidelines because solder joints are not fully exposed with qfn packages, any touch-up is limited. for defects underneath the package, the whole package must be removed. because reflow of adjacent parts is not desirable during rewo rk, the proximity may complicate the rework process. because of the product-dependent complexities, the following provides only a guideline and a starting point for the development of a successful rework process for this package. the rework process comprises the following steps: 1. component removal the first step in removal of the component is the reflow of solder joints attaching the component to the pcb board. ideally the reflow profile for part removal and attachment should be the same, but this is not always possible. ? heat the board from the top side of the component. ? use a special nozzle to direct the heating in the component area. ? minimize the heating of adjacent components. ? start with an air velocity of 15 to 20 liters per minute. ? avoid excess heating and pad liftoff. 2. site redress after removing the component, clean the site properly. ? use de-soldering braid to remove excess solder. ? once the residual solder is removed, clean the lands with solvent. the solvent is usually specific to the type of paste used in the original assembly. 3. solder paste printing to achieve a uniform and precise deposition, use a miniature stencil specific to the component. avoid tinning the lands, because the amount of solder applied to the lands cannot be controlled. 4. component placement and attachment although this type of package does display self-centering abilities, use care in its placement. ideally, the reflow profile for part removal and attachment should be the same, but this is not always possible. heat the board from the top side of the component.
electrical characteristics stm7007 14/27 doc id 022239 rev 1 2 electrical characteristics note: the values in this section are preliminary, and subject to change. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 environment maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 dc electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 pci, miscellaneous 3.3v interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 phy 1.2v and 2.5v interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ac electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 differential interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1 recommended operating conditions note: operation beyond recommended conditions is neither recommended nor guaranteed. table 5. recommended operating conditions parameter minimum typical maximum units notes vdd1v2 1.14 1.2 1.26 v core voltage vdd2v5 2.375 2.5 2.625 v antifuse charge-pump vdd3v3 3.0 3.3 3.6 v i/o voltage for pcie interface vddt1v2 1.14 1.2 1.26 v transmit channel vdd vddr1v2 1.14 1.2 1.26 v receive channel vdd vddpll1v2 1.14 1.2 1.26 v pll core vddpll2v5 2.375 2.5 2.625 v pll ta 0 - 70 c ambient temperature
stm7007 electrical characteristics doc id 022239 rev 1 15/27 2.2 absolute maximum ratings caution: stresses beyond those listed in ta b l e 6 may cause permanent damage to the device; because these are stress ratings, functional operation is not implied at these or any other conditions beyond those indicated in table 5 on page 14 . exposure to the conditions listed in ta b l e 6 for extended periods may affect device reliability. 2.3 environment maximum ratings 2.4 power dissipation table 6. absolute maximum ratings (1) 1. these are stress ratings, no t functional operation ratings. parameter minimum(v) maximum (v) notes vdd1v2 -0.5 1.5 core voltage vdd2v5 -0.5 3.0 antifuse charge-pump vdd3v3 -0.5 4.0 pci io ring vddt1v2 -0.5 1.5 transmit channel vdd vddr1v2 -0.5 1.5 receive channel vdd vddpll1v2 -0.5 1.5 pll core vddpll2v5 -0.5 3.0 pll table 7. environment maximum ratings parameter minimum maximum units notes esd hbm ? 2000 v human body model esd cdm ? 500 v charged device model tstorage -40 150 c storage temperature table 8. power dissipation typical mode symbol/mode current (ma) for power rails (v) total (mw) notes 3.3 2.5 1.2 l0 - af programming 2 48 216 385.8 l0 - bulk 2 17 222 315.5 l0 - average 2 17 173.4 257.18 average power, assuming 10% duty cycle (0.1 * l0-bulk + 0.9 * l0-idle) l0 - idle 2 17 168 250.7 l0s 2 17 139 215.9 l1 - clkreq# asserted 2 17 126 200.3 clock power management disabled l1 - clkreq# deasserted 1 3 20 34.8 clock power management enabled
electrical characteristics stm7007 16/27 doc id 022239 rev 1 2.5 dc electrical specifications 2.5.1 pci, miscell aneous 3.3v interfaces note: 1 while i/o is in high impedance state 2 does not include current flowing through termination resistors. 2.5.2 phy 1.2v and 2.5v interfaces table 9. 3.3v interface pin dc specifications parameter symbol test condition minimum typical maximum units notes input low level vil -0.3 ? 0.8 v input high level vih 2.0 ? 0.3 + vdd3v3 v output low level vol 8 ma ? ? 0.4 v output high level voh 8 ma vdd3v3 - 0.4 ? ? v input leakage current iil 0 stm7007 electrical characteristics doc id 022239 rev 1 17/27 2.6 ac electrical specification 2.7 differential interface electrical characteristics table 11. pci express clock input parameter description mini mum typical maximum units fref pcie pin refclkp, refclkn the clock must be compliant with the lvds input driver level. 99.97 100 100.03 mhz table 12. pcie interface driver and receiver characteristics description symbol minimum maximum units baud rate br 2.5 gbps unit interval ui 399.88 400.12 ps baud rate tolerance brtol -300 300 ppm driver parameters differential peak to peak output voltage vtxpp 800 1200 mv minimum tx eye width ttxeye 0.750 ui differential return loss trldiff 10 db common mode return loss trlcomm 6 db dc differential tx impedance ztxdiff 85 115 receiver parameters differential peak to peak voltage vrxpp 0.175 1.2 v minimum rx eye width trxeye 0.4 ui differential return loss trldiff 10 db common mode return loss rrlcomm 6 db dc differential rx impedance zrxdiff 85 115 dc single-ended input impedance zrxdc 40 60
electrical characteristics stm7007 18/27 doc id 022239 rev 1 2.7.1 pcie test circuit when measuring transmitter output parameters, c_tx is an optional portion of the test/measurement load. when used, the value of c_tx must be in the range of 75 to 200 nf. c_tx must not be used when the test/measurement load is placed in the receiver package reference plane. figure 8. pcie test circuit
stm7007 pcb layout guidelines doc id 022239 rev 1 19/27 3 pcb layout guidelines pcb routing of rx/tx differential signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pcb power and ground decoupling guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 the stm7007 uses high speed, low voltage differential signal pairs for the pcie interface. for a successful board design, follow the placement and layout guidelines in this chapter for critical signals. additional application notes may be provided for more detailed requirements. the stm7007 is designed for optimized wiring for both a motherboard or pci express mini-card form factor. pin locations of the crit ical high speed lvds signals are designed to support a seamless flow from the stm7007 to the upstream host controller. see also, figure 1: device pinout, top view .
pcb layout guidelines stm7007 20/27 doc id 022239 rev 1 3.1 pcb routing of rx/tx differential signals ensure that the board design meets the following criteria: to avoid skew, make signal pair lengths equal from the ball to the connector: txp length = txn length, an d rxp length = rxn length lengths may differ if required to compensate for length mismatch due to poor package substrate routing. route signal pairs in parallel ensure a 100 differential impedance trace: ? route signals on an external layer with a full or partial ground plane layer as the next internal adjacent layer. a partial ground plane must cover and exceed the area below the tx and rx signal routing. ? between the package pin and the pci-express connectors, ensure equal signal trace interspace distance on each pair along the entire trace length. to avoid crosstalk: ? separate tx and rx pairs a minimum of 5 mm, with no other signals interleaved. ? if several ports are routed, do not route the tx and rx traces of each port one above the other on different layers. do not use: ? right angles or 45-degree trace angles; curved traces are preferred ?pcb vias make all traces: ? as direct and straight as possible ? as short as possible. signal line attenuation may be compensated for by selecting a higher buffer swing, but if the largest swing is specified for the application, there is no capacity for swing compensation. if components (such as ac coupling capacitors) are required on the high speed signal traces, choose the smallest smd packages and place them close to connectors. pcb trace crossing: if two differential traces from different ports must cross, cross the traces at 90 o (perpendicular) to each other.
stm7007 pcb layout guidelines doc id 022239 rev 1 21/27 3.1.1 example: pcb impedance calculation the pcb manufacturer should provide the board designer with all relevant parameters for calculating trace impedance: trace thickness trace width pcb material, giving e r distance between layer 1 and internal layer 2 coating thickness example calculation the calculator shown in figure 9 gives a theoretical z diff = 101.6 . the pcb manufacturer double-checked with its tools and a more complex calculator, taking into account the cross-section form of the top layer trace and the coating used. the pcb manufacturer?s calculation gives a theoretical z diff = 100.2 . figure 9. ultraz calculation for differential pair impedance differential pair rout ed on top layer (1) trace width: 7 mils inter-space trace distance: 7 mils ground plane on internal layer 2, giving 5.9 mils dielectric height (e r = 3.9) trace thickness: 40 m = 1.6 mils.
pcb layout guidelines stm7007 22/27 doc id 022239 rev 1 3.2 pcb power and ground decoupling guidelines figure 10. power map all grounds : connect directly to the pcb common ground plane power pins vddr1v2 and vddt1v2 : directly connect to the board?s 1.2v common supply dedicated to the phy decouple locally using: ? murata ferrite blm15ag121 or equivalent ?1.0 f ceramic capacitor ?0.1 f rf capacitor (low series access resistor) ?0.01 f rf capacitor (low series access resistor) power pin vddpll1v2 : directly connect to the board?s 1.2v common supply dedicated to the phy filter locally using: ?1 resistor ?10 f ceramic capacitor ?0.1 f rf capacitor (low series access resistor) ?0.01 f rf capacitor (low series access resistor) power pin vdd2v5 : directly connect to the board?s 2.5v common supply dedicated to the phy filter locally using: ?1 resistor ?1.0 f ceramic capacitor ? 100 pf rf capacitor (low series access resistor) ? 10 nf rf capacitor (low series access resistor) 3.3v i/o rail pci express mini card connector for mobile form-factor: support for clock power management (clkreq#) pci express connector for atx/mini-atx form-factor: no support for clock power management (clkreq#) pci express connector reg reg 1.2v rx 2.5v antifuse 2.5v pll 1.2v core 1.2v pll 1.2v tx stm7007
stm7007 pcb layout guidelines doc id 022239 rev 1 23/27 power pin vddpll2v5 : directly connect to the board?s 2.5v common supply dedicated to the phy filter locally using: ?30 resistor (5% maximum tolerance) ?0.1 f rf capacitor (low series access resistor) ?0.01 f rf capacitor (low series access resistor) 3.3 power sequencing the stm7007 requires proper supply voltage and pgood (power good) sequencing for the internal power-on-self-test and the antifuse blocks. figure 11 shows the timing and level requirements. the primary requirement for this device is pgood timing; pgood must provide a valid status of the supply voltages during power sequencing. the pgood signal: remains inactive until all voltages are within their required tolerance bands during power up goes inactive before the supply voltages exit their required tolerance bands during power down the first indication that power-down sequencing is occurring, is the dropping of the 3v3 input supply voltage. the pgood input pin and the perst# input pin are logically combined internally to ensure the proper reset state of the device during sequencing. the 2v5 and 1v2 regulators must be sourced by the 3v3 supply such that the recommended order of supply sequencing at power up is 1v 2 first and then 2v5, and at power down 2v5 drops first, and then 1v2. because of an internal esd protection diode, it is expected that when the 1v2 is applied to the vddpll1v2 pin, the vddpll2v5 pin will sour ce voltage at a level equal to the 1v2 voltage minus the forward voltage drop of a diode. to limit the diode current, and to provide lowpass filtering of the pll 2v5 power source, place a 30 , 5% resistor between the vdopll2v5 pin and the 2v5 source. position the bypass capacitors close to the vddpll2v5 pin (pad).
pcb layout guidelines stm7007 24/27 doc id 022239 rev 1 figure 11. power up / down timing requirements 3v3 input 1v2 2v5 pgood power up power down 950 mv min. 100 mv max. 2.25 v min. 10 us min. 800 mv max. 2.0 v min. 3.6 v max. 3.60 v max. 3.00 v min. 2.25 v min. 2.75 v max. 800 mv max. 10 us min. 100 mv max. 2.25 v min. 3.00 v min. perst# (alternate) 1.32 v max. 1.08 v min. 10 us min. 2.0 v min. 3.6 v max. 800 mv max. 3.00 v min. 0.0 us typ. 10 us min. 800 mv max. 1.08 v min.
stm7007 ordering information doc id 022239 rev 1 25/27 4 ordering information when ordering parts, use the information below and contact your local stmicroelectronics sales office, field applications engineer, or manufacturer?s representative for further information. table 13. stm7007 ordering information order code package type note stm7007 32-pin lga 5x5 commercial rohs and halogen free package
revision history stm7007 26/27 doc id 022239 rev 1 5 revision history table 14. document revision history date revision changes 06-oct-2011 1 initial release.
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